This invention relates to active bias circuits.
As is known in the art, active bias circuits have a wide range of applications. One such active bias circuit is described in U.S. Pat. No. 5,793,194 entitled xe2x80x9cBias Circuit Having Process Variation Compensation and Power Supply Variation Compensationxe2x80x9d, inventor Edward T. Lewis, issued Aug. 11, 1998, assigned to the same assignee as the present application, the entire subject matter thereof being incorporated herein by reference. Some of these applications include battery-operated cellular telephones and wireless Local Area Networks (WLANS). More particularly, the bias circuit may be used to supply bias current to transmitter and receiver amplifiers used therein.
As also known in the art, in battery operated cellular telephone and wireless Local Area Networks (WLANS) applications, it is frequently desirable to reduce the power in the transmitter amplifier when the phone is in the receive mode. One technique suggested to provide such power reduction is to place a transistor switch in series with VDD and the drain of the RF amplifying transistor. Power is saved by decoupling VDD from the drain of the RF amplifying transistor. This has several major disadvantages however. While the transistor switch being in series with the RF transistor must be in a conducting mode during the desired amplification. When such transistor switch is conducting a voltage drop is produced across such transistor switch thereby reducing amplification power. Further, the transistor switch requires additional components to bias the switch and extra logic to turn it off. Also, the drain of the RF transistor requires it to be bypassed with very large capacitors. Thus, if switching is performed at this point in the circuit, one must charge and discharge these capacitors (when turning on and off the transistor switch). Such charging and discharging however requires time, in the order of tens on microseconds. Applications, such as wireless Local Area Networks (WLANS) require this switching action to take place in under a microsecond.
In accordance with the invention, an integrated circuit biasing network is provided for producing a predetermined level of bias current. The bias network includes a field-effect transistor having a gate, a source and a drain. The transistor produces a level of bias current corresponding to a predetermined input gate-source voltage applied to the field effect transistor. A control circuit is provided. The control circuit is connected to the field effect transistor and provides a current through a control current path to produce the field effect transistor input voltage. A compensation circuit is connected to the control circuit. The compensation circuit includes a compensation transistor of the same type as the field effect transistor. The compensation circuit operates the compensation transistor to divert current from said control current path whereby process variations cause the compensation transistor to draw a current of a magnitude to provide an input voltage to the field effect transistor to enable such field effect transistor to produce said predetermined level of bias current. A transistor switch is provided having a first and second electrode. Conductivity between such first and second electrodes is controlled by an xe2x80x9conxe2x80x9d/xe2x80x9coffxe2x80x9d control signal fed to a control electrode of such transistor switch. One of such first and second electrodes is coupled to the gate of the field effect transistor and the other one of the first and second electrodes is coupled to a predetermined reference potential. The transistor switch is placed in a conduction condition by the xe2x80x9conxe2x80x9d/xe2x80x9coffxe2x80x9d control signal to couple the gate of the field effect transistor to such reference potential during an xe2x80x9coffxe2x80x9d condition of the control signal. Such coupling to the reference potential turns the field effect transistor to a non-conducting state during such xe2x80x9coffxe2x80x9d condition. The transistor switch is placed in a non-conductive condition to decouple the gate of the field effect transistor from such reference potential during an xe2x80x9conxe2x80x9d condition of the control signal to enable the field effect transistor to amplify a signal fed to the gate thereof during such xe2x80x9conxe2x80x9d condition.
With such an arrangement, the turn off circuit is at the RF gate, which do not require as much bypassing. Therefore, the arrangement is able to turn of the RF transmitter within the 1 microsecond requirement.
In one embodiment, the reference potential is coupled to the control circuit.
In one embodiment, the field effect transistor, the compensation transistor and the transistor switch are depletion mode field effect transistors.
In one embodiment, the compensation circuit is coupled between a second reference potential and the first-mentioned reference potential.